Verification Engineer salaries in Aust, GLS

At least 3-5 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM. Work on debug failing test cases to root cause.

Building and inspecting our products. The successful applicant will also be able to demonstrate an example of an electronic or mechanical project that they have…

£26,500 a year

Contribute to the continuous improvement of platforms and processes, creating and validating dashboards and queries while staying up to date with platform…

You will also be the point of contact within the project and to our customer to support the team regarding Systems Engineering, Validation and Verification…

At least 1-2 years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience).

Applications are invited from candidates who may hold HNC/HND in a relevant engineering discipline in concert with significant and demonstrable subject matter…

14 days ago