Senior/staff digital design engineer Work, Jobs in Frenchay, Gls (with Salaries)

Senior/Staff Digital Design Engineer
OLIX —Bristol
- £194,000 a year
- Full-time
- AI
- Python
Senior/Staff Design for Test Engineer
OLIX —Bristol
- £321,000 a year
- Full-time
- Scripting
- AI
- Python
Senior/Staff Analog Design Engineer - SerDes
OLIX —Bristol
- £317,000 a year
- Full-time
- Doctoral degree
- Engineering
- Master's degree
Senior Software Engineer (Oracle Technologies)
Office for National Statistics —Newport
- £44,050 - £47,121 a year
- Full-time
- Hybrid work
- Oracle
- SQL
- Presentation skills
5d
Senior Dynamics Developer
Intellectual Property Office —Newport
- £47,766 - £58,575 a year
- Part-time
- Hybrid work
- Azure
- DevOps
- Presentation skills
- Annual leave
Senior Lecturer in Engineering Infrastructure and Sustainability
University of the West of England —Frenchay
- £46,049 - £58,225 a year
- Full-time
- Doctoral degree
- Engineering
- University
- Annual leave
7d
Senior Data Engineer
Office for National Statistics —Newport
- £41,985 a year
- Full-time
- Hybrid work
- SQL
- Presentation skills
- Python
6d
Senior Data Engineer - (GCP)
Office for National Statistics —Newport
- £41,985 a year
- Full-time
- Hybrid work
- Presentation skills
- Python
6d
Senior Lecturer in Structural Engineering
University of the West of England —Frenchay
- £46,049 - £58,225 a year
- Full-time
- Doctoral degree
- Engineering
- University
- Annual leave
7d
Senior Software Engineer (AWS Cloud Technologies)
Office for National Statistics —Newport
- £44,050 - £47,121 a year
- Full-time
- Hybrid work
- AWS
- Presentation skills
- JavaScript
5d
Lead Electronics Design Engineer
Renishaw —Wotton-under-Edge
- Up to £60,000 a year
- Full-time
- Hybrid work
- Engineering
- Free parking
- Employee assistance programme
Principal Water Quality Scientist/ Modeller
AECOM —Bristol
- Full-time
- Hybrid work
- Master's degree
- Project management
- Scripting
Senior Mechanical Engineer - Water / Wastewater
Egis —Bristol
- Microsoft Excel
- Engineering
- Master's degree
- Annual leave
Senior Energy Engineer
Airbus Operations Limited —Bristol
- Full-time
- Hybrid work
- Travel
- HVAC
- Contracts
- Free parking
13d
Senior Process Engineer - Nuclear
AECOM —Bristol
- Full-time
- Hybrid work
- Engineering
- Bachelor's degree
Senior Electronic Design and Firmware Engineer
Systems Engineering and Assessment Ltd —Frome
- Up to £67,000 a year
- Call to connect
- Hybrid work
- Communication skills
- Python
- Free parking
- Annual leave
Domain Expert - Responsible AI, Ethics & Assurance
Methods Business and Digital Technology —Bristol
- £80,000 - £120,000 a year
- Full-time
- Hybrid work
- Sales
- Travel
- Mentoring
- Employee assistance programme
Quick apply
Associate Hydrologist
AECOM —Bristol
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Bachelor's degree
13d
Senior Nuclear Safety Case Engineer
AECOM —Bristol
- Full-time
- Hybrid work
- Engineering
- Master's degree
- Mentoring
Associate Risk Manager / Project Director
AECOM —Bristol
- Full-time
- Hybrid work
- Project management
- Bachelor's degree
- Team management

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senior/staff digital design engineer jobs near frenchay, gls

Senior/Staff Digital Design Engineer

OLIX
Bristol

Apply Now

Job details

Full-time
£194,000 a year

Qualifications

MATLAB
FPGA
NumPy
VHDL
Electrical engineering
Verilog
Simulink
SystemVerilog
AI
Python
Digital design

Full job description

About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role

We are seeking highly skilled and motivated Senior/Staff Digital Design Engineers with a strong focus on CMOS digital design to take end-to-end ownership of high-speed, real-time data-processing silicon, from early algorithm modelling to verified RTL and silicon bring-up. You will join a multidisciplinary group creating next-generation hardware where digital, optical and mixed-signal domains intersect. The ideal candidate will have a strong background in electrical engineering and semiconductor physics, along with a passion for developing reliable, high-performance digital circuits that drive breakthrough AI hardware.

Responsibilities

Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes
Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC
Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off
Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification
Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets
Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions
Mentor junior engineers, lead design reviews and champion best‑practice design methodologies

Skills & Experience

7+ years of hands‑on digital design for high‑performance ASICs or SoCs, including ownership of at least one product that processes a continuous real‑time data stream
Proven success closing timing on multi‑hundred‑MHz to multi‑GHz clock domains and integrating high‑speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)
Expertise with industry‑standard EDA flows: RTL synthesis, CDC/RDC, STA, power‑intent (UPF/CPF), lint, and gate‑level simulation
Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab
Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed‑point analysis and test‑vector generation
Solid grounding in digital signal‑processing concepts, computer‑architecture fundamentals and semiconductor device physics
Excellent communication and cross‑functional collaboration abilities; thrives in a fast‑moving, ambiguous environment

Nice to have

Tape‑out experience at 22 nm or below
Knowledge of coherent optical links or photonic‑electronic co‑design.
Familiarity with AI/ML workloads, systolic arrays or tensor‑processing architectures.
Contributions to open‑source RTL, verification frameworks or FPGA boards.

Compensation & Equity

Competitive Salary: Commensurate with your experience, skills, and location
Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it
Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security

Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

Compensation Range: $194K

Apply Now

Refine Your Search

senior/staff digital design engineer jobs in frenchay, gls

Senior/Staff Digital Design Engineer

Senior/Staff Design for Test Engineer

Senior/Staff Analog Design Engineer - SerDes

Senior Software Engineer (Oracle Technologies)

Senior Dynamics Developer

Senior Lecturer in Engineering Infrastructure and Sustainability

Senior Data Engineer

Senior Data Engineer - (GCP)

Senior Lecturer in Structural Engineering

Senior Software Engineer (AWS Cloud Technologies)

Lead Electronics Design Engineer

Principal Water Quality Scientist/ Modeller

Senior Mechanical Engineer - Water / Wastewater

Senior Energy Engineer

Senior Process Engineer - Nuclear

Senior Electronic Design and Firmware Engineer

Domain Expert - Responsible AI, Ethics & Assurance

Associate Hydrologist

Senior Nuclear Safety Case Engineer

Associate Risk Manager / Project Director

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