Verification Engineer salaries in Wales

At least 1-2 years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience).

At least 3-5 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM. Work on debug failing test cases to root cause.

14 days ago

Ensure design information is managed and issued in a timely and controlled manner to meet procurement and construction requirements.

Up to £55,000 a year

7 days ago

Crosstrain across other areas within Cwmbran test facility to provide strength in depth during absences, support laboratory customers and technicians, and…

Competitive package (Grade 2-3, £25,000 - £40,000 dependent on experience). Supporting the writing of test procedures for build-to-print and development…

£25,000 - £40,000 a year

Hybrid working model: typically 3 days per week in our Bristol office, with flexibility around project needs. Our Client is a Bristol-based engineering company…

£24,850.59 - £69,675.98 a year