Programming Work, Jobs in Pathhead, Fif (with Salaries)

ASIC Design Engineer
AST SpaceMobile —Edinburgh
- Doctoral degree
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Principal Product Engineer - Custom Layout & Virtuoso Applications
Cadence Design Systems —Edinburgh
- Full-time
- Engineering
- Master's degree
- Bachelor's degree
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- Life insurance
Senior Breeding Programme Manager
Genus Plc —St. Andrews
- Full-time
- Hybrid work
- Doctoral degree
- Computer literacy
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Analog Devices —Edinburgh
- Full-time
- Doctoral degree
- Computer Science
- Engineering
Design Verification Engineer (EDI)
Cirrus Logic —Edinburgh
- Full-time
- Hybrid work
- Computer Science
- Engineering
- Master's degree
Head of Electrical
Aaron Services —Bathgate
- Full-time
- Management
- Quality control
- Business
- Annual leave
- Employee assistance programme
Design Verification Engineer (NWB)
Cirrus Logic —Edinburgh
- Full-time
- Hybrid work
- Computer Science
- Engineering
- Master's degree
Head of Electrical
Sureserve —Bathgate
- Management
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- Annual leave
- Employee assistance programme
Quick apply
Mixed Signal Modelling and Verification Engineer (#GNEG4)
Cirrus Logic —Edinburgh
- Full-time
- Hybrid work
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- Master's degree
Postdoctoral Research Associate in Cold-Water Coral in-Silico Reef Models
Heriot Watt University —Edinburgh
- £37,694 - £47,389 a year
- Full-time
- Hybrid work
- Doctoral degree
- Engineering
- Research
- Annual leave
7d
Senior Design Manager
AECOM —Edinburgh
- Full-time
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Civil Engineer - Water / Principal Scour Management
Amey Ltd —Perth
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- Master's degree
- Annual leave
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Highways Supervisor
Amey Ltd —Kinross
- Weekend availability
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- Annual leave
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Lead Chef
Everyman Media —Edinburgh
- £12.37 - £13.77 an hour
- Full-time
- Cooking
- Employee assistance programme
- Employee discount
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Ion Beam Services —Bathgate
- Microsoft Powerpoint
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- Up to 50% travel
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ASIC Design Engineer

AST SpaceMobile -
Edinburgh

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Job details

Qualifications

MATLAB
Doctoral degree
Signal processing
Stakeholder collaboration
Stakeholder liaison
Engineering
Master's degree
SoC
Bachelor's degree
Scripting
Technical writing
Multidisciplinary collaboration
SystemVerilog
Electrical Engineering

Full job description

AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.

Position Overview

We are seeking an ASIC Design Engineer to contribute to the design and implementation of complex silicon solutions used in AST's space‑based communications systems.

The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‑value silicon that is core to AST's mission of "Connecting the unconnected" - delivering the world's first space‑based mobile broadband network.

The team works collaboratively to define and build next‑generation silicon, exploring advanced silicon technologies to continuously improve performance, capability, and efficiency. This is a hands‑on environment where silicon decisions directly impact AST's ability to deliver a global communications network from space.

In this role, you will focus on high‑quality RTL development, micro‑architecture definition, and close collaboration across engineering disciplines. You will work alongside architecture, verification, and system teams—both internal and external—to deliver robust, high‑performance ASIC and SoC designs from concept through tape‑out.

Key Responsibilities:

Create high‑quality micro‑architecture specifications and RTL code.
Contribute to SoC integration and subsystem development.
Work with internal and external stakeholders, including architecture, verification, and software teams.
Participate in design reviews, providing technical input.
Ensure alignment with requirements and design best practices.

Qualifications

Education:

BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

Experience:

Deep knowledge of hardware and digital design fundamentals.
Strong SystemVerilog knowledge.
Experience with SoC integration.
Prior experience on complex RTL designs such as high‑speed I/O, CPUs, accelerators, or complex network‑on‑chip implementations.
Ability to write clear, high‑quality micro‑architecture specifications.
Competency in Python scripting or programming.

Preferred Qualifications:

Master's or PhD degree in a relevant technical discipline.
Experience on large SoC / ASIC designs.
RF knowledge is a strong plus.
Understanding of digital signal processing.
Experience with MATLAB is a plus.
Background in communications or mobile silicon system design.

Soft Skills:

Ability to collaborate closely with architecture, verification, software, and system teams.
Ability to work effectively with internal and external stakeholders.
Ability to provide technical input during design reviews.

Technology Stack:

SystemVerilog
Python scripting or programming
MATLAB

Physical Requirements

Ability to work in a standard office environment and use a computer for extended periods.
Occasional travel may be required to visit suppliers or other AST SpaceMobile design centers.

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands.

AST SpaceMobile is an Equal Opportunity, at will Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Apply Now

Refine Your Search

programming jobs in pathhead, fif

ASIC Design Engineer

Principal Product Engineer - Custom Layout & Virtuoso Applications

Senior Breeding Programme Manager

Grid Insights Architect

Design Verification Engineer (EDI)

Head of Electrical

Design Verification Engineer (NWB)

Head of Electrical

Mixed Signal Modelling and Verification Engineer (#GNEG4)

Postdoctoral Research Associate in Cold-Water Coral in-Silico Reef Models

Senior Design Manager

Civil Engineer - Water / Principal Scour Management

Highways Supervisor

Lead Chef

Software Engineer

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