Verification Engineer salaries in Whitchurch, BST

At least 3-5 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM. Work on debug failing test cases to root cause.

You will guarantee all these products function well with each other and with the software to enable our partners to develop outstanding systems.

£73,500 - £99,500 a year

At least 1-2 years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience).

Act as the first escalation and troubleshooting point for productivity vendor solutions (e.g., Microsoft), owning investigation and issue resolution for vendor…

Up to £28 an hour

Competitive package (Grade 2-3, £25,000 - £40,000 dependent on experience). Supporting the writing of test procedures for build-to-print and development…

£25,000 - £40,000 a year

In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.

£73,500 - £99,500 a year