Algorithm engineer Work, Jobs in Leigh, Gtm (with Salaries)

FPGA Embedded Engineer
Space Systems Ltd —Manchester
- £27,000 - £40,000 a year
- Full-time
- Engineering
- C++
- In-person
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5h
Technical Solutions Architect
Zippd —Manchester
- Full-time
- English
- SQL
- AWS
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Senior GenAI Engineer
Anaplan —Manchester
- Computer Science
- Master's degree
- Bachelor's degree
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Senior Verification Engineer - ISP
Arm —Manchester
- £73,500 - £99,500 a year
- Hybrid work
- Machine learning
- Scripting
- Leadership
C++ Algorithms Engineer
ALTEN —Manchester
- £40,000 - £65,000 a year
- Full-time
- Computer Science
- Military
- Engineering
- Employee assistance programme
- Life insurance
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Staff Verification Engineer
Arm —Manchester
- £97,300 - £131,700 a year
- Hybrid work
- Machine learning
- Mentoring
- Scripting
- Relocation assistance
Principal Verification Engineer - Video
Arm —Manchester
- £126,200 - £170,800 a year
- Hybrid work
- Machine learning
- Mentoring
- Scripting
Debugger Software Engineer
Arm —Manchester
- £55,300 - £74,800 a year
- Hybrid work
- Java
- C++
- Machine learning
2d
Security Engineer
Barclays —Knutsford
- Azure
- Java
- AWS
7d

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FPGA Embedded Engineer

Space Systems Ltd -
Manchester

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Job details

Permanent | Full-time
£27,000 - £40,000 a year
5 hours ago

Qualifications

MATLAB
Image processing
Signal processing
FPGA
Engineering
Electronics Engineering
VHDL
Git
Verilog
C++
C
Simulink
Computer Engineering
ARM
Electrical Engineering
AI

Full job description

About the Role

We are looking for an FPGA and Embedded Engineer to join the team and take ownership of hardware software co-design across our payload and ground segment systems. You will work on FPGA preprocessing pipelines, AI inference on edge hardware, and signal processing chains bridging the gap between the RF subsystem and the software platform. The work is hands on, technically demanding, and directly shapes what flies or deploys.

Responsibilities

Designing and implementing FPGA logic for signal preprocessing, data conditioning, and high speed data interfacing using Xilinx UltraScale+ and Zynq devices.
Developing and maintaining firmware and embedded software for satellite payload and ground subsystems in C and C++.
Implementing AI inference pipelines on NVIDIA Jetson Orin NX integrating TensorRT-optimised models for real-time image processing, object detection, and onboard EO analytics.
Building FPGA-based image processing pipelines including preprocessing, pixel-level operations, compression, and data formatting for downlink.
Working in Vivado and Vitis for FPGA design, synthesis, implementation, and hardware-software co-design workflows.
Using MATLAB Simulink and HDL Coder for model-based design, algorithm development, and automatic HDL generation.
Integrating FPGA and embedded subsystems with the wider satellite platform interfacing with RF chains, ADCs, DDCs, and communication controllers.
Supporting hardware-in-the-loop (HIL) testing, debugging with hardware tools, and generating verification and validation evidence.
Writing and maintaining technical documentation including design descriptions, test reports, and interface control documents.

Requirements

Degree in Electronic Engineering, Embedded Systems, Computer Engineering, or a related field.
Strong FPGA design experience VHDL or Verilog, RTL design, simulation, and implementation on Xilinx devices.
Hands-on experience with Xilinx UltraScale or UltraScale+ families and Vivado toolchain.
Embedded C/C++ development on ARM or RISC-based processors, including bare-metal and RTOS environments.
Experience with AI inference on edge hardware NVIDIA Jetson, TensorRT, or equivalent edge AI deployment.
Familiarity with image processing pipelines pixel processing, feature extraction, or computer vision on constrained hardware.
Understanding of hardware-software co-design and partitioning between FPGA fabric and embedded processors.
Experience with MATLAB and Simulink for algorithm development or system modelling.
Git-based development workflow and structured documentation practice.
Software Defined Radio (SDR) experience GNU Radio, Ettus USRP, RFSoC, or equivalent platforms.
Signal processing knowledge digital filters, FFT, modulation schemes, ADC/DAC interfacing, or link budget analysis.

Pay: £27,000.00-£40,000.00 per year

Work Location: In person

Quick apply

Refine Your Search

algorithm engineer jobs in leigh, gtm

FPGA Embedded Engineer

Technical Solutions Architect

Senior GenAI Engineer

Senior Verification Engineer - ISP

C++ Algorithms Engineer

Staff Verification Engineer

Principal Verification Engineer - Video

Debugger Software Engineer

Security Engineer

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