Asic physical design engineer Work, Jobs in Thurleigh, Bdf (with Salaries)

ASIC PHYSICAL DESIGN ENGINEER
Vhunt4u —Cambridge
- CAD
- Engineering
- Master's degree
CAD Physical Design Engineer
Apple —Cambridge
- Computer Science
- Engineering
- Master's degree
3d
GPU Physical Design Engineer
Apple —Cambridge
- Engineering
- Bachelor's degree
- Electrical Engineering
Experienced GPU Top Level Physical Design Engineer
Apple —Cambridge
- Electrical Engineering
Sr. ASIC Design Engineer, Blink/Ring ASIC Team
Evi Technologies Limited —Cambridge
- Full-time
- Doctoral degree
- Engineering
- English
Principal Engineer- Design Implementation
Microchip Technology —Cambridge
- Full-time
- Engineering
- Bachelor's degree
- Travel
8d
Staff Digital IC Design Engineer
Power Integrations —Cambridge
- Full-time
- Doctoral degree
- Engineering
- Laboratory experience
- Employee stock purchase plan
- Employee assistance programme
4d
Graduate Silicon Engineer
Graphcore —Cambridge
- C++
- AI
- Python
- Annual leave
- Employee assistance programme
7d
Principal Opto-Electronics Engineer
Microsoft —Cambridge
- £91,800 - £154,700 a year
- Full-time
- Remote
- Azure
- Doctoral degree
- Engineering
Principal Optical Packaging Engineer
Microsoft —Cambridge
- £91,800 - £154,700 a year
- Full-time
- Remote
- Azure
- Doctoral degree
- Engineering
Senior Optical Packaging Engineer
Microsoft —Cambridge
- £73,800 - £121,300 a year
- Full-time
- Azure
- Doctoral degree
- Engineering
20h

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CAD Physical Design Engineer
Apple —Cambridge
The job includes hands-on work & impact on all layers of the design cycle, from infrastructure related automation for design efficiency through developing…
3d
GPU Physical Design Engineer
Apple —Cambridge
Manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

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asic physical design engineer jobs near thurleigh, bdf

Work Location : Cambridge, Bangalore, London, Malaysia, San Jose

Work Expertise : 5 Years - 15 Years

Desired Profile :

Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PD
Experience in Top / Block level ASIC PnR implementation (RTL to GDSII).
Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
Excellent communication and presentation skills, experience in collaborating with global teams.
Experience in hierarchical designs and/or Low Power implementation is an advantage.
Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
Ability to provide mentorship and guidance to junior engineers and be an effective team player.
Expertise in Cadence Innovus, Tempus, Calibre
Required relevant expertise for India and Malaysia is 5+ years and 10+ years of relevant expertise for other locations

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